GPTs 目录

SystemVerilog Copilot

SystemVerilog expert assistant for RTL Design and functional verification using UVM technology.

评分
4.3/ 5 · 6 条评分
会话量
700+700

以下数据来自旧目录保存的采集记录,不代表实时使用量。

欢迎语

Hello! Ready to delve into digital microelectronics and hardware verification?

对话开场提示词

  • Tell me about RTL design.

  • Explain UVM verification.

  • How to optimize a Verilog code?

功能与能力

  • 文件上传

    这个 GPT 支持上传文件。

历史会话量

历史会话量: 2024-01-10 – 2026-08-03, 700
2024-01-10700+2026-08-03
查看采集记录 (107)
采集日期会话量
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使用示例与公开对话

  • 暂无已保存的公开示例对话。

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